With development of high-capacity memory devices, nonvolatile memory devices are becoming increasingly important. An example of the nonvolatile memory device is a flash memory device. The flash memory devices can preserve information stored in a memory cells even without power being supplied to the device. Additionally, information can be erased from the flash memory at high-speed.
As an example, U.S. Pat. No. 6,566,195 to Rudeck provides a method and a structure for an improved floating gate memory cell. The nonvolatile memory cell by the Rudeck patent includes a first insulating layer formed on a substrate; a shallow trench isolation (STI) region having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate; a second insulating layer formed on the first conducting layer; and a second conducting layer formed on the first insulating layer.
In the field of flash memory technology development, memory cell structure has been continuously improved in various ways. Examples of such improved cell structures include a stack gate cell, a split gate cell, a source side injection cell, etc. Particularly, the stack gate cell has a multi-layer structure that a floating gate and a control gate are stacked in sequence. In the stack gate cell, a source/drain region is formed by channel hot electron injection(CHEI) and a program operation is performed in the drain side and an erase operation is performed through Follower-Nordheim tunneling in the source side. The stack gate cell is very small in size and, therefore, is largely used as a unit cell of flash memory devices.
A cell array is an important factor determining a type of a flash memory device together with a memory device structure, an erasing method, and a programming method. Among various cell array structures, an AND-type cell array can embody the densification and the high-performance operation of a flash memory.
FIG. 1 is a schematic diagram illustrating cell array of a conventional AND-type flash memory device. FIG. 2 shows a layout of the flash memory device of FIG. 1. FIG. 3 is a cross-sectional view of FIG. 2 taken along a line A–A′.
Referring to FIGS. 1 through 3, in an AND-type flash memory device, a floating gate 24 and a control gate 26 are layered on a substrate 20 including a device isolation layer 22 and a source/drain region 28 is formed at both sides of the floating gate 24 in the substrate 24. A thin tunnel oxide 23 is formed between the substrate 20 and the floating gate 24 and a gate oxide 25 is formed between the floating gate 24 and the control gate 26. Such an AND-type flash memory device embodies densification by sharing bit line contacts and source lines in a plurality of cells and suppresses the occurrence of disturb during program operation through parallel connection and the layered bit lines and source lines.
However, a conventional AND-type flash memory device has a high density of interconnection in a diffusion layer and, in particular, has a low coupling ratio due to the reduction of cell size according to high-integration. Such a low coupling ratio may cause an increase in internal voltage within the AND-type flash memory device.
As a conventional method of increasing the coupling ratio in fabricating a flash memory cell, U.S. Pat. No. 6,153,494 to Hsieh et al. provides a method for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. The method disclosed in the Hsieh et al. patent comprises depositing a high or thick layer of nitride; forming a shallow trench isolation (STI) through the nitride layer into the substrate; filling the STI with isolation oxide; removing the nitride thus leaving behind a deep opening about the filled STI; filling conformally the opening with a first polysilicon layer to form a floating gate; forming interpoly oxide layer over the floating gate; forming a second polysilicon layer to form the control gate; and forming the self-aligned source of the stacked-gate flash memory cell.
As another example, U.S. Pat. No. 6,326,263 to Hsieh discloses a method of fabricating a flash memory cell having a self-aligned floating gate structure and an enhanced coupling ratio characteristic. The method disclosed in the Hsieh patent comprises providing a substrate having a tunneling oxide layer, a defined first polysilicon layer, and a sacrificial layer defining an active region; performing an etching process using the sacrificial layer as a mask to form a STI pattern; forming a dielectric layer that fills the STI pattern; performing a planarization process to remove the dielectric layer over the sacrificial layer; performing a first etch back process to remove a pre-selected thickness of the dielectric layer over the STI pattern; forming a second polysilicon layer; performing a second etch back process to form a spacer connecting with the first polysilicon layer; removing the sacrificial layer; forming an insulating layer on the surface of the spacer and the first polysilicon layer; forming a control gate on the insulating layer; and performing an ion implantation process to form a source and a drain on the substrate within the active region.